1. Field of the Invention
The present invention relates to a package and a fabrication method thereof, and in particular, to an improved integrated chip package and the fabrication method thereof.
2. Background of the Related Art
FIG. 1 is a perspective view showing a partly cut away PMEB (Plastic Molded Extended Bump) type chip-size semiconductor package. As shown in this drawing, a metal wiring pattern 13 is formed to connect a plurality of chip pads 12 formed on the semiconductor chip 11 with internal bump bonding pads 17. Conductive internal bumps 16 are attached on the internal bump bonding pad 17 and tapes (not shown) are attached to the top surfaces of the conductive internal bumps 16. Then the semiconductor chip 11 is surrounded and molded with a molding resin 14. When the tapes are removed, the top surfaces of the internal bumps 16 are exposed. A solder paste is applied on the internal bumps 16, external electrode bumps 15 are placed thereon and the external bumps 15 and the internal bumps 16 are attached through an infrared reflow process, resulting in a completed PMEB-type chip-size semiconductor package, a description of which was published at the "SEMICON JAPAN '94 SYMPOSIUM" held by the MITSUBISHI corporation in Japan.
FIG. 2 is a cross-sectional view of a bump electrode in FIG. 1. The chip pads 12 are formed on the top surface of the semiconductor chip 11, and a passivation film 18 is formed on the semiconductor chip 11, except on the top surface of the chip pads 12. The metal wiring pattern 13 is formed on the chip passivation film 18, wherein one end of the metal wiring pattern 13 is connected to the chip pad 12 and the other end thereof 13 is connected to the internal bump bonding pad 17. A polyimide film 10 is formed on the above construction, except at the internal bump connecting pads 17, and the internal bumps 16 are attached to the exposed internal bump connecting pads 17 by means of a solder adhesive 20 composed of Pb or Sn. A molding resin 14 encapsulates the semiconductor chip 11 by surrounding the same on the entire surface of the above construction except for the top surface of the internal bumps 16, and the external bumps 15 are attached to the internal bumps 16.
As described above, a bump bonding pattern for transmitting an electrical signal of the chip pads 12 to the external bumps 15 is formed through a separate formation process of a metal wiring pattern (a pre-assembly process). The metal wiring pattern 13 is formed from the chip pads 12 of the semiconductor chip 11 to the internal bump connecting pads 17 to be electrically connected, respectively, and the conductive internal bumps 16 are attached to the internal bump connecting pads 17. The molding resin 14 surrounds and seals the above entire construction, and the external bumps 15, serving as external leads, are attached to the internal bumps 16 to form a completed chip-size semiconductor package. Although the PMEB-type chip-size semiconductor package allows the overall size of the entire semiconductor package to be smaller, a separate formation process for the metal wiring pattern (pre-assembly process in the published data) and an bonding process for internal and external bumps are necessary. Further, the fabrication process is complicated and the fabrication cost is increased.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.